SN74LVC1G00DPWR

• Available in the Ultra Small 0.64-mm2
  Package (DPW) With 0.5-mm Pitch
• Supports 5-V VCC Operation
• Inputs Accept Voltages to 5.5 V
• Provides Down Translation to VCC
• Max tpd of 3.8 ns at 3.3 V
• Low Power Consumption, 10-μA Max ICC
• ±24-mA Output Drive at 3.3 V
• Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back Drive Protection
• Latch-Up Performance Exceeds 100 mA
  Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 1000-V Charged-Device Model (C101)

This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G00 performs the Boolean function
Y = A × B or Y = A + B in positive logic.

The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.

The SN74LVC1G00 is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm.